1. Technical Field
This invention generally relates to computer systems, and, more specifically, to a buffering scheme used in a computer system for improving system performance by providing concurrent operation of CPU cycles, cycles to memory, and cycles to a local bus under specific circumstances.
2. Background Art
A modern microcomputer system typically comprises a CPU coupled to a local bus, and coupled to a main memory via a memory bus. The local bus is typically connected to an expansion bus, such as a typical ISA, EISA, or Micro-channel.RTM. bus. One example of a local bus is the Peripheral Component Interconnect (PCI) bus commonly used in microcomputers based on the Intel Pentium .RTM. CPU. One of the most efficient ways to improve performance in a computer system is to use posted data buffers. For example, a host bridge interposed between the CPU and the PCI bus may include posted data buffers to store several CPU-to-PCI write operations, thereby freeing up the CPU to continue processing while the host bridge becomes a PCI bus master by arbitrating for and obtaining ownership of the PCI bus, and then passes the data to the appropriate PCI device. Posted data buffers may also be used when the host bridge is acting as a slave device on the PCI bus, such as when another PCI device wants to write data to main memory. The posted data buffers within the host bridge can store data for multiple PCI writes to main memory (usually to consecutive locations), thereby freeing up the PCI bus for other PCI devices to use.
One example of a posted data buffer is disclosed in U.S. Pat. No. 5,224,214 "Buffers for Gathering Write Requests and Resolving Read Conflicts by Matching Read and Write Requests" (issued Jan. 29, 1993 to Rosich and assigned to Digital Equipment Corp.), which is incorporated herein by reference. Other types of data buffers are known, as shown in U.K. Pat. No. GB 2 248 128 A "A Single Board Computer" (issued Mar. 25, 1992 to Coates et al. and assigned to Online Computing Limited); and U.S. Pat. No. 5,239,636 "Buffer Memory Subsystem for Peripheral Controllers" (issued Aug. 24, 1993 to Dujari et al. and assigned to Advanced Micro Devices, Inc.), which are incorporated herein by reference.
Two problems associated with posted data buffers are data coherency and possible deadlock conditions. Maintaining data coherency is essential to assure that data in main memory is updated with the contents of any posted data buffers containing the data prior to another device accessing the data. For example, when a host bridge is acting as a slave on the PCI bus, it may receive write data from a PCI master and store the data in its posted data buffers, followed by the PCI master releasing the PCI bus. At that point, the PCI master will signal the CPU via interrupt that the transfer has taken place, and the CPU will then retrieve the data from main memory. To maintain data coherency, the data in the posted data buffers must be transferred to main memory before the CPU is allowed to read the data. Otherwise, erroneous data will be returned to the CPU.
Another problem with posted buffers is the possibility of deadlock. Potential deadlock conditions exist when a first PCI device holds data to be written to a second PCI device in its posted data buffers, and the second PCI device also wants to send data to the first PCI device. If both devices cannot receive new data until they have transmitted their write data, then a deadlock occurs. Two devices that may become deadlocked are interlocked devices. For example, an expansion bus bridge coupled to the PCI bus and to a typical expansion bus (such as ISA, EISA, Micro-channel.RTM., etc.) may become interlocked with other PCI devices. Once the expansion bus bridge wins arbitration of the PCI bus for an expansion bus device, it cannot relinquish the PCI bus if the intended PCI target cannot accept the data. If the PCI target device has posted data to send to the expansion bus that it must transmit before it can accept new data, a deadlock condition exists. If either of the expansion bus bridge and the PCI target device could receive data while waiting to transmit write data, the deadlock would not exist.
One possible solution to avoid the deadlock of interlocked devices is to use side band signals (i.e., signals that are not part of the PCI bus protocol) to force a flush of all posted write data buffers in interlocked PCI devices to memory, and to acknowledge that this flush has been completed. The two needed signals are FLUSH and ACKNOWLEDGE. The PCI bus arbiter would signal FLUSH before it granted the bus to the expansion bus bridge so that each interlocked device that has write data in its posted data buffers can arbitrate and transmit all the data in its buffers. Once the interlocked devices have emptied and disabled their buffers, ACKNOWLEDGE signals the expansion bus bridge to grant the expansion bus to the requesting device and gain ownership of the PCI bus for it. Then the transfer can take place with assurance that all interlocked devices can accept new data. This solution requires the use of at least two pins for the side band signals, potentially increasing the cost of the devices that need the side band signals since higher pin counts usually require larger, more expensive packages. In addition, since these side band signals are outside of the PCI specification, care must be taken to ensure that any interlocked devices support the same protocol or risk potential deadlocks within the computer system, adding complexity to the system.
The disadvantages of the side band signal solution to the data coherency and deadlock problems that arise when using posted data buffers result in the need for a solution that uses no side band signals (i.e., conforms to PCI bus specifications), and that maximizes concurrency in the computer system while assuring data coherency and avoiding deadlock conditions.